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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CTIDEVARCH, CTI Device Architecture register</h1><p>The CTIDEVARCH characteristics are:</p><h2>Purpose</h2>
        <p>Identifies the programmers' model architecture of the CTI component.</p>
      <h2>Configuration</h2><p>CTIDEVARCH is in the Debug power domain.
    </p>
        <p>If the CTI is CTIv1, this register is <span class="arm-defined-word">OPTIONAL</span>. If the CTI is CTIv2, this register is mandatory.</p>

      
        <p>Arm recommends that the CTI is CTIv2.</p>

      
        <p>In an Armv8.5 compliant implementation, the CTI must be CTIv2.</p>

      
        <p>If this register is not implemented, <a href="ext-ctidevaff0.html">CTIDEVAFF0</a> and <a href="ext-ctidevaff1.html">CTIDEVAFF1</a> are also not implemented.</p>
      <h2>Attributes</h2>
        <p>CTIDEVARCH is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="11"><a href="#fieldset_0-31_21">ARCHITECT</a></td><td class="lr" colspan="1"><a href="#fieldset_0-20_20">PRESENT</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16-1">REVISION</a></td><td class="lr" colspan="16"><a href="#fieldset_0-15_0">ARCHID</a></td></tr></tbody></table><h4 id="fieldset_0-31_21">ARCHITECT, bits [31:21]</h4><div class="field"><p>Defines the architecture of the component. For CTI, this is Arm Limited.</p>
<p>Bits [31:28] are the JEP106 continuation code, <span class="hexnumber">0x4</span>.</p>
<p>Bits [27:21] are the JEP106 ID code, <span class="hexnumber">0x3B</span>.</p>
      <p>Reads as <span class="binarynumber">0b01000111011</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-20_20">PRESENT, bit [20]</h4><div class="field">
      <p>Indicates that the DEVARCH is present.</p>
    
      <p>Reads as <span class="binarynumber">0b1</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-19_16-1">REVISION, bits [19:16]<span class="condition"><br/>When FEAT_DoPD is implemented:
                        </span></h4><div class="field"><p>Revision.</p>
<p>Defines the architecture revision of the component.</p><table class="valuetable"><tr><th>REVISION</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>First revision.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>As <span class="binarynumber">0b0000</span>, and also adds support for <a href="ext-ctidevctl.html">CTIDEVCTL</a>.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-19_16-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field"><p>Revision.</p>
<p>Defines the architecture revision of the component.</p><p>All other values are reserved.</p>
<p>Reads as <span class="binarynumber">0b0000</span>.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-15_0">ARCHID, bits [15:0]</h4><div class="field"><p>Defines this part to be an Armv8 debug component. For architectures defined by Arm this is further subdivided.</p>
<p>For CTI:</p>
<ul>
<li>Bits [15:12] are the architecture version, <span class="hexnumber">0x1</span>.
</li><li>Bits [11:0] are the architecture part number, <span class="hexnumber">0xA14</span>.
</li></ul>
<p>This corresponds to CTI architecture version CTIv2.</p>
      <p>Reads as <span class="hexnumber">0x1A14</span>.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h2>Accessing CTIDEVARCH</h2><h4>CTIDEVARCH can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>CTI</td><td><span class="hexnumber">0xFBC</span></td><td>CTIDEVARCH</td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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